Method for fabrication semiconductor device

ABSTRACT

The object of this invention is to provide a method for fabricating a semiconductor device in which the yield and productivity are improved. In the method for fabricating a semiconductor device according to the invention, a plasma etching system is prepared which includes a vacuum chamber  1,  a susceptor  7  arranged in the vacuum chamber  1  to place a wafer  8,  a gas introducing means  2  to introduce the material gas into the vacuum chamber and a high-frequency power introducing means  6.  The gas introduced into the vacuum chamber by the gas introducing means  2  is converted into a plasma by the high-frequency power, and a plurality of holes are selectively formed in the oxide film  23  of a main wafer surface in a plasma atmosphere. In the hole forming step, light  15  having a continuous spectrum is irradiated on a flat portion and a hole portion of the main surface of the semiconductor wafer thereby to measure the reflectivity change in the flat portion and the hole portion.

TECHNICAL FIELD

The present invention relates to the field of the semiconductortechnique, or in particular to a method of fabricating a semiconductordevice including the step of forming contact holes of an interlayerinsulating film.

BACKGROUND ART

The process of fabricating a semiconductor device includes the step offorming contact holes by dry etching using plasma in an interlayerinsulating film (an insulating film containing silicon oxide as a maincomponent) formed on the main surface of the wafer and filling asemiconductor or metal in the contact holes. In forming the contactholes, it is indispensable for an improved yield of the semiconductordevice to fully open without any etch stop before exposure of thesurface of the base semiconductor region or the underlying wiring. Inview of the ever decreasing size of the contact hole and the resultingincrease in the difficulty of etching, it is very important forexecuting a desired etching process to grasp the progress of the etchingprocess or especially the etching depth accurately and reflect it in theprocessing conditions.

The situation in which the etching to form the contact holes is stoppedmidway and the underlying semiconductor region or the base wiring is notexposed is called an opening failure. In the prior art, in order tosuppress the yield reduction due to the opening failure, it has been thepractice to specify the cause of a defect by observing the cross sectionunder SEM (scanning electron microscope) or inspecting the openingfailure by the potential contrast method.

In the conventional method, however, a sample for the inspection devicesuch as SEM is required to be prepared by actually sampling out a waferfrom the lot. This requires a non-product wafer on the one hand andconsumes the time of feedback to the fabrication process on the otherhand, thereby reducing the productivity. Incidentally, the non-productwafer is defined as a wafer not directly contributing to the fabricationof a semiconductor device.

Now that the hole diameter has been decreased to almost less than 100nm, the light in the wavelength range of ultraviolet to visible lighthardly enters the pattern bottom without the effect of the patternboundary, and the interference waveform measurement method using thelight path length difference between the upper part and the bottom ofthe pattern cannot acquire a sufficiently practicable signal-to noiseratio (S/N).

As disclosed in JP-A-2000-131028 and JP-A-2001-284323, a means availableto monitor the etching depth of the contact hole in real time is amethod to determine the etching depth from the interference waveform dueto the difference of the light path length between the upper part andthe bottom of the pattern.

DISCLOSURE OF THE INVENTION

The object of this invention is to provide a method for fabricating asemiconductor device capable of improving the yield and theproductivity.

Representative aspects of the invention disclosed in this applicationare briefly explained below.

According to this invention, there is provided a method for fabricatinga semiconductor device by preparing a plasma etching system including avacuum chamber, a susceptor arranged in the vacuum chamber to mount asemiconductor wafer, a gas introducing means for introducing a materialgas to the vacuum chamber and a high-frequency power introducing means,the method comprising the step of converting to a plasma the gasintroduced into the vacuum chamber by the gas introducing means andforming a plurality of holes selectively on a main surface of thesemiconductor wafer in the plasma atmosphere, comprising the steps ofirradiating light having a continuous spectrum on a flat portion and ahole portion of the main surface of the semiconductor wafer andmeasuring the change in reflectivity of the flat portion and the holeportion, in or after the step of forming the holes.

According to this invention, in the etching process, the opticalcharacteristics are measured in simple way so that the etching conditionor especially the etching depth of each contact hole is monitored innondestructive way thereby to make possible the early lot stop and thefeedback to the processing conditions. As a result, the productivity isimproved even for the logic products typically like DRAM (dynamic randomaccess memory) requiring the volume production of scant items or thescant production of multiple items.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram showing a dry etching device having theetching depth inspection function used in a first embodiment of theinvention.

FIG. 2 is a partial sectional view of a wafer according to the firstembodiment of the invention.

FIG. 3 is a plan view of a wafer according to the first embodiment ofthe invention.

FIG. 4 is a diagram for explaining the scanning process at the detectionlight radiation position according to the first embodiment of theinvention.

FIG. 5 is a characteristic diagram showing the wavelength dependency ofthe reflectivity of the flat portions and the hole portion and thewavelength shift amount of the interference peak according to the firstembodiment of the invention.

FIG. 6 is a characteristic diagram showing the relation between thewavelength shift amount of the interference peak and the etching timeaccording to the first embodiment of the invention.

FIG. 7 is a characteristic diagram showing the relation between thewavelength shift amount and the number of wafers processed upon completeetching according to the first embodiment of the invention.

FIG. 8 is a schematic diagram showing a plasma etching system ofmultichamber type used in the first embodiment of the invention.

FIG. 9 is a schematic diagram showing an unload lock chamber with theetching depth inspection function used in the second embodiment of theinvention.

FIG. 10 is a characteristic diagram showing the relation between themeasurement accuracy and the measurement frequency of the impedancemeasurement according to the second embodiment of the invention.

FIG. 11 is an equivalent circuit diagram showing the capacitance betweenthe upper electrode and the lower electrode in the flat portion of themain wafer surface according to the second embodiment of the invention.

FIG. 12 is an equivalent circuit diagram showing the capacitance betweenthe upper electrode and the lower electrode in the hole portion of themain wafer surface according to the second embodiment of the invention.

FIG. 13 is a characteristic diagram showing the relation between theetching depth and ΔC according to the second embodiment of theinvention.

FIG. 14 is a schematic diagram showing a dry etching device with theetching depth inspection function used in a third embodiment of theinvention.

FIG. 15 is a characteristic diagram showing the relation between theadded O₂ flow rate and the maximum aspect ratio generated by an etchstop according to the third embodiment of the invention.

FIG. 16 is a sequence diagram showing the O₂ flow rate control stepaccording to the third embodiment of the invention.

FIG. 17 is a partial sectional view showing a semiconductor device inthe HARC forming step according to the third embodiment of theinvention.

FIG. 18 is a partial sectional view showing a semiconductor device inthe SAC forming step according to the third embodiment of the invention.

BEST MODE FOR CARRYING OUT THE INVENTION

This invention is explained in more detail with reference to theaccompanying drawings..

EMBODIMENT 1

A configuration of a dry etching device with the etching depthinspection function used in an embodiment of the invention is shown inFIG. 1. With this etching device, a material gas is introduced into avacuum chamber through a gas introduction pipe 2 and a shower plate 3,and a plasma is formed by the high-frequency electric field generated bya high-frequency power supply 6. The internal pressure of the vacuumchamber 1 (etching processing chamber) is reduced by a vacuum exhaustmeans (not shown) of high exhaustion capacity such as a turbo-molecularpump and regulated by a conductance valve 21. The vacuum chamber 1contains a lower electrode 7, on which a semiconductor wafer 8 isplaced. The semiconductor wafer 8 is formed of, for example, singlecrystal silicon (Si), which contains therein a shallow-grooved isolationregion and a semiconductor region (active region) defined by theshallow-grooved isolation region. The main surface of the semiconductorwafer 8 is formed with an insulating layer (interlayer insulating film)of silicon dioxide (specifically, a TEOS film). The lower electrode 7 isconnected with a high-frequency bias power supply 9. The frequency ofthe high-frequency bias power supply 9 is 400 kHz to 1.56 MHz, orpreferably, 800 kHz. The interior of the vacuum chamber 1 is maintainedin a pressure-reduced environment, and ions in the plasma are drawn inby the Vpp (peak-to-peak) voltage of about 0.5 kV to 2 kV generated inthe lower electrode 7 by the high-frequency bias power supply 9 therebyto etch the insulating film.

Next, the etching depth inspection function (the etching depth measuringunit) built in the etching device is described in detail.

The etching depth measuring unit according to this embodiment isarranged above the vacuum chamber 1. Specifically, the ceiling of thevacuum chamber 1 has a quartz window 14 to introduce detection light 15.White light (continuous spectrum of 350 nm or more) enters the quartzwindow from a Xe lamp 11 as the detection light through a lens 13. Acomponent of the detection light is radiated on the wafer 8, and thereflected light is reflected on a beam splitter through the same lightpath and enters a detection system. The other components of thedetection light are led directly to the detection system through a beamsplitter 12 as reference light. The detection system is configured of aspectrometer 16 and a diode array 17 to instantaneously measure thewavelength distribution of the intensity of the incident light and thereflected light. The lens 13 is arranged on a vertically movable stage(not shown) to focus the light on the wafer 8. These component parts ofthe etching depth instrument unit are arranged on an XY movable table 18movable horizontally. The XY movable table 18 is connected electricallyto a computer 20 through a D/A converter 38. The computer 20 is alsoelectrically connected to the diode array 17 through an A/D converter19.

This embodiment includes a light source, an optical system and adetection system as a set to measure the flat portion and the holeportion in real time. In order to improve the inspection throughput,however, two sets of the light source, the optical system and thedetection system may be provided, one used for measuring the holeportion and the other for measuring the flat portion.

A measuring method using the etching depth measuring unit configured asdescribed above is explained below with reference to FIGS. 1 to 5. FIG.2 is a partial sectional view of a wafer in the state in which an oxidefilm 23 is deposited on the wafer (Si substrate 40) and a photo patternis transferred to the oxide film 23 using a resist mask 22 having aplurality of holes to form contact holes. As shown in FIG. 2, a resistmask 22 formed on the oxide film 23 (insulating film) includes a portionhaving a plurality of hole patterns and a flat portion not formed withthe hole pattern. FIG. 3 is a plan view of a wafer formed with holepatterns. The patterns 24 making up an IC chip are arranged in a grid onthe main surface of the wafer 8. A hole pattern (a plurality of holes)is formed in each chip pattern 24. FIG. 4 is a plan view showing a partof the interior of the chip pattern in which hole patterns areclustered.

First, in FIG. 1, the position of the flat portion not formed with thehole patterns is specified from the computer 20 supplied with the dataof the wafer patterns 24 shown in FIG. 3, and the position of thedetection light for measuring the flat portion is determined by the XYmovable table 18. The detection light 15 is radiated at the measurementposition on the wafer 8 from the Xe lamp 11 through the lens 13.Specifically, as shown in FIG. 2, detection light 15A enters at rightangles or diagonally with a predetermined angle to a flat portion 22Anot formed with any hole pattern. In the process, the vertically movablestage is moved vertically to focus the light at the measurement positionon the wafer. Using the spectrometer 16 and the diode array 17, thewavelength dependency of the reflectivity providing the ratio ofintensity between the incident light and the reflected light ismeasured, and stored as a reference data in the computer 20. Inmeasuring the flat portion, interference occurs due to the phase shiftbetween the light reflected on the surface of the resist mask 22 and thelight reflected on the boundary between the resist 22 and the oxide film23.

Next, the actual measurement position is output from the computer 20,the XY movable table 18 is driven and the position of the detectionlight is provisionally determined. Like in the flat portion, thedetection light 15 is radiated at the measurement position on the waferfrom the Xe lamp through a lens. Also, the vertically movable table ismoved vertically to focus the light at the measurement position on thewafer. Specifically, as shown in FIG. 2, detection light 15B enters ahole portion 22B formed with the hole patterns. In the process, thelight enters the hole portion 22B on the same conditions as when thelight enters the flat portion 22A. Specifically, as long as the lightenters the flat portion 22A at right angles thereto, so does the lightenter the hole portion 22B at right angles thereto.

As shown in FIG. 4, the XY movable table is scanned and the wavelengthdependency of the reflectivity of the detection light is measured ateach point. The amount of wavelength shift with respect to theinterference peak position of the reference data already acquired iscalculated, and the XY movable table is fixed at the position associatedwith the maximum shift. Through this process, even with a pattern havinga large pitch of the hole portion like a logic product, a predeterminedmaximum number of holes can be always accommodated in a detection lightradiation area 25 for each wafer, and therefore the measurement accuracycan be improved.

According to this embodiment, the wavelength of the detection light isset to at least twice the hole diameter of the subject to be measured,and therefore the hole portion is considered to become progressivelyporous with the advance of etching, resulting in the wavelength shift ofthe interference peak as shown in FIG. 5. The amount of shift Δλ of theinterference peak with respect to the reference data represents thevolume change of the measurement area.

Assuming that the thickness of the oxide film and the resist film of thehole portion is equal to that of the flat portion and the hole diameteris calculated from the pattern data, then the volume change amount isconverted to the etching depth. Of the steps described above, the stepsother than the step of determining the measurement position of the flatand hole portions are repeated during the etching operation. Thus, theetching depth can be measured in real time.

Next, the method of calculating the resist selectivity is explained. Thereference data on the wavelength dependency of the reflectivity at theflat portion acquired already is compared with the theoretical curvedata calculated based on the multiple reflection interference modelusing the thickness of the oxide film having a wafer thickness structurestored in advance. In this way, the prevailing resist film thickness canbe calculated. The difference with the initial film thicknessconstitutes the reduced resist amount at the particular time point. Onthe other hand, as already explained, the etching depth at the holeportion is determined from the wavelength shift amount of theinterference peak position with respect to the reference data, andtherefore, the resist selectivity can be determined by dividing theetching depth by the reduced resist amount.

FIG. 6 shows the relation between the etching time and the wavelengthshift amount. With the progress of the etching operation, as indicatedby curve a, the wavelength shift amount increases with respect to theetching time. In the case where an etch stop occurs midway, however, thewavelength shift amount remains at a constant value from that time pointas shown by curve b. According to this embodiment, in the case where thecurve b is obtained during the etching operation, for example, it isdetermined that an etch stop has occurred, and as shown in FIG. 7, theprocess is continued by changing the recipe to high porosity conditions.As a result, the metal burial against the opening failure, i.e. thecontact failure can be prevented. In this way, a system can beconstructed in which while maintaining the throughput, the yield andproductivity are improved.

This embodiment is explained above with reference to a system comprisingthe light source, the optical system and the detection system as a set.A similar effect is obtained, however, by dividing the detection lightfrom the light source through an optical element such as a beam splitterand thus providing two sets of the light source, the optical system andthe detection system. Further, the system can be used as a monitor ofsecular variations by measuring the reflectivity alone in the holeportion for each wafer.

Also, according to this embodiment, the configuration in which theetching depth is measured in real time was explained. This etching depthmeasuring unit can be installed without regard to the gas atmosphere.Specifically, the etching depth measuring unit can be installed not onlyin the vacuum chamber for conducting the etching operation, but also inan unload lock chamber 29 shown in FIG. 8, for example, where the waferafter etching is carried and stays for a certain length of time. As aresult, the etching depth can be monitored without reducing thethroughput. By monitoring the etching depth of the contact holes, theprocess is stopped for the semiconductor wafer next to be etched or thefeedback to the etching process conditions is made possible.

After that, a metal such as tungsten (W) or copper (Cu) is buried in thethrough holes thus formed.

EMBODIMENT 2

With reference to FIGS. 9 to 13, an embodiment in which the etchingdepth is observed by measuring the electrostatic capacitance isexplained.

According to this embodiment, the measuring means is installed in theunload lock chamber or, for example, in the unload lock chamber 29 shownin FIG. 8. The unload lock chamber is an intermediate vacuum chamber fordischarging the wafer processed in the etching chamber to the wafercassette.

In FIG. 9, a measuring upper electrode (second electrode) 30 isinstalled in opposed relation to the wafer surface in the ceilingportion of the unload lock chamber 29. This measuring upper electrode 30is electrically isolated from the vacuum chamber by an insulating member31. The end portion of an upper electrode 30 opposed to the wafer formsa circular flat surface of 0.1 mm to 3 mm in diameter. The upperelectrode 30 is arranged on a vertically movable stage 32 in such amanner that the interval with the wafer surface is set to 0.1 μm to 50μm. In order to monitor this interval, a laser displacement gauge 33 ismounted at the forward end of the electrode. A measuring lower electrode(first electrode) 35 with the wafer placed thereon, on the other hand,is arranged on an XY movable table 36 movable in both X and Y directionsand can measure an arbitrary position. The XY movable table 36 iselectrically connected to the computer 20 through an A/D converter 38A.The laser displacement gauge 33 is electrically connected to thecomputer 20 through an A/D converter 19. The lower electrode 35 includesa plurality of protruded electrodes 34 having a sharp forward endthrough the oxide film on the opposite surface of the wafer to assureconstant contact. An impedance meter 37 is electrically connectedbetween the upper electrode 30 and the lower electrode 35 to measure thecapacitance between the electrodes. The impedance meter 37 iselectrically connected to the computer 20 through the A/D converter 38C.

Next, the method of measuring the etching depth is explained.

First, as shown in FIG. 9, the wafer 8 after etching is transported andarranged on the lower electrode 35. Since the opposite surface of somewafers is formed with an oxide film, the contact is secured by applyingthe protruded electrodes against it. In this case, by measuring theresistance between two protrusions each time the wafer is arranged, thereproducibility of the contact on the reverse surface is guaranteed. Anymeans other than a small protruded electrode capable of securing contactpositively, however, is of course covered by the scope of thisembodiment.

Next, based on the pattern data of the wafer stored in advance in thecomputer 20, the XY movable table 36 is driven so that the electrode 30is moved to the measurement position of the flat portion having nopattern. After that, the output value of the laser displacement gauge 33is fed back while driving the vertically movable stage 32 thereby to fixthe interval between the surface of the wafer 8 and the surface of theupper electrode 30 at a set value. FIG. 10 shows the relation betweenthe measurement accuracy of the impedance meter and the measurementfrequency. According to this embodiment, the measurement frequency isset to 100 kHz to minimize the measurement accuracy.

The impedance is measured at the measurement position on the flatportion. The measurement, as shown in FIG. 11, is equivalent to thecombined capacitance of the capacitance Cg between the electrode and thewafer, the resist capacitance Cm and the oxide film capacitance Cfconnected in series.

Next, the position of the upper electrode 30 is changed to the holeportion providing the measurement position by the XY movable table 36.As in the measurement on the flat portion, the combined capacitance ismeasured from the impedance measurement. As in the first embodiment, theholes formed by etching are assumed to become progressively porousmacroscopically. As shown in FIG. 12, a parallel capacitance can beassumed between the capacitance Ch of the hole portion and thecapacitance Cf of the portion (around the hole portion) filled with theoxide film. Since the combined capacitance is reduced by etching, therelation between the difference ΔC with the value for the flat portionand the etching depth as shown in FIG. 13 is obtained. In this case, thethickness of the oxide film is assumed to be 2 μm, the open area ratioto be 20% and the electrode-wafer interval to be 1 μm. In this case, ΔCincreases with the etching depth, and assumes 0.47 (pF) for the etchingdepth of 2 m. This is a value equal to about 5% of the combinedcapacitance and sufficiently measurable.

Next, the improvement of reproducibility of the measurement position isexplained. As explained in the first embodiment, the XY movable tablewith the wafer arranged thereon is scanned in the neighborhood of themeasurement position of the hole portion. At each position, the combinedcapacitance is measured, and the difference between the minimum of thisvalue and the combined capacitance of the flat portion is assumed to bethe true value of ΔC. With this process, even for a pattern having largepitches of the hole portions like a logic product, the number of holesaccommodated in the measurement range of the upper electrode can bemaintained at a constant and maximum value for each wafer, and thereforethe measurement accuracy can be improved.

As long as the above-mentioned inspection shows that the through holesare formed positively by etching, such metal as tungsten (W) or copper(Cu) is buried in the through holes thus formed. In other words, theprocess of burying the metal in the through holes is executed. In thecase where the through holes are an opening failure, the etchingconditions for the next semiconductor wafer to be etched are changed toa recipe assuring positive opening.

Also in this embodiment, as in the first embodiment, the resistselectivity can be calculated. The combined capacitance for the flatportion obtained earlier is compared with the theoretical combinedcapacitance calculated from the wafer thickness structure stored inadvance, so that the resist film thickness at the particular time pointcan be calculated. Thus, the difference with the initial film thicknessgives the reduced resist amount after complete etching. As alreadyexplained, on the other hand, the etching depth is determined from thedifference between the combined capacitance of the flat portion and thecombined capacitance of the hole portion, the oxide film thickness, theopening area and the film structure between the electrode and the wafer.By dividing this value by the reduced resist amount, therefore, theresist selectivity can be determined.

EMBODIMENT 3

With reference to FIGS. 14 to 18, a more specific method of fabricatinga semiconductor device according to an embodiment is explained below.The process of forming contact holes requiring a high-accuracy etchingwith the ever decreasing size of the semiconductor device (LSI) is shownin FIGS. 17 and 18.

First, FIG. 17 is a sectional view showing the process of formingcontact holes called HARC (high aspect ratio contact hole) in theinterlayer insulating film (specifically, the TEOS film). To form HARC,a hole as deep as 2 μm with a diameter of 0.13 μm or, in the future, notmore than 0.1 μm is required to be formed in the interlayer insulatingfilm 23B. In the process, the dry etching process causes an openingfailure or a contact failure due to improper shape such as a tape in thehole bottom often leading to a lower yield.

FIG. 18 is a sectional view showing the process of forming contact holescalled SAC (self-align contact). In forming SAC, a silicon nitride film42 protecting a gate electrode 41 is not etched, but the silicon oxidefilm 23A is dry etched thereby to expose the main surface of a siliconsubstrate (more specifically, the semiconductor region such the sourceor drain) 40. To obtain the selectivity of the silicon nitride film 42and the silicon oxide film 23, a sophisticate deposit control operationis required. Delicate variations of the etching conditions would causean opening failure or the unsatisfactory shape such as a taper of thecontact portion.

The method of evaluating the etching result described in the first orsecond embodiment is used for the process of forming the contact holesshown in FIG. 17 or 18.

These processes of forming contact holes also employ the etching deviceshown in FIG. 14. An embodiment thereof is explained below.

An Ar/C₅F₈/O₂ mixed gas is used as a material gas, and the gas pressureis set to 2 Pa. Under this condition, assume that a minuscule hole(contact hole CH) having a diameter of 0.1 μm shown in FIG. 17 isetched. The flow rate of O₃ added and the maximum aspect ratio causingan etch stop hold the relation shown in FIG. 15. As a result, it isunderstood that the etch stop is remarkably improved with the O₂ flowrate and the region for suppressing the etching exists in theneighborhood of the aspect ratio 4. Specifically, it has become clearthat to suppress the additional O₂ flow rate to required minimum andthus improve the mask selectivity, the stepped etching operation iseffective in which the O₂ flow rate is increased to about 4 in aspectratio and subsequently is reduced.

According to this embodiment, as shown in FIG. 14, the basicconfiguration is explained above in the first embodiment with referenceto FIG. 1. Especially, to control the O₂ flow rate, the gas flowmeter 10is electrically connected to a recipe control computer 39 through an A/Dconverter 38. According to this embodiment, the etching is conducted atthe O₂ flow rate control step shown in FIG. 16. The relation between theaspect ratio and the O₂ flow rate added is input beforehand in therecipe control computer 39. In this way, the problem described above canbe obviated without regard to the change in etching rate due to secularvariations. Although only the gas flow rate control system is describedabove, this control system is also applicable to the control operationof other external parameters including the gas pressure, high-frequencypower and high-frequency bias power.

After the step of forming contact holes, what is called the plug formingstep is executed in which a metal is buried in the contact holes CH.After the plug forming step, the wiring forming step is executed by thewell-known sputtering or photolithography.

Incidentally, in the process of fabricating the semiconductor device,the SAC forming step shown in FIG. 18 is executed before the HARCforming step shown in FIG. 17. The HARC forming step shown in FIG. 18 isexecuted on the insulating film 23B formed on the interlayer insulatingfilm 23A shown in FIG. 18.

According to this invention explained specifically above with referenceto embodiments, in the etching method to form contact holes by etching,the mask selectivity of the resist or the like and the etching depth aremonitored nondestructively and simplified way in the etching process orin the process of transporting the wafer from the etching chamber aftercomplete etching, thereby making an early lot stop or feedback to theprocess conditions. As a result, the productivity can be improved in theproduction of DRAM or the like products requiring thesmall-volume-multi-item production as well as thelarge-volume-scant-item production required for logic products.

INDUSTRIAL APPLICABILITY

According to this invention, in the process of fabricating asemiconductor device or especially in the step of forming contact holes,the etching depth and the mask selectivity of the resist or the like canbe monitored and feedback is made possible nondestructively in simplemethod during the etching process or during the wafer transportationfrom the etching chamber after the etching process. As a result, theyield and productivity of the semiconductor device are improved.

1. A method of fabricating a semiconductor device, using a plasmaetching system including a vacuum chamber, a susceptor arranged in thevacuum chamber for mounting a semiconductor wafer, a gas introducing amaterial gas to the vacuum chamber and a means for introducinghigh-frequency power, the method comprising the steps of producingplasma from a gas introduced into the vacuum chamber by the gasintroducing means using the high-frequency power; forming a plurality ofholes selectively on a main surface of the semiconductor wafer in anatmosphere of the plasma; during or after the hole forming step,irradiating the light having a continuous spectrum in a flat portion anda hole portion of the main surface of the semiconductor wafer andmeasuring the amount of shift along the direction of the wavelength axisbetween the reflectivity of detection light for the flat portion and thereflectivity of detection light for the hole portion: and calculatingthe depth of the hole portion based on the wavelength axis directionshift amount, film thickness data and hole pattern.
 2. A method forfabricating a semiconductor device as defined in claim 1, wherein thelight enters the main surface of the semiconductor wafer at right anglesor diagonally thereto, and the reflectivity is measured from the ratioof intensity between the incident light and the reflected light. 3.(canceled)
 4. A method for fabricating a semiconductor device as definedin claim 1, wherein the main surface of the semiconductor wafer has aninterlayer insulating film, and the plurality of the holes are formed inthe interlayer insulating film.
 5. A method of fabricating asemiconductor device comprising: (1) a step of forming an insulatingfilm on the semiconductor substrate and a mask on the insulating film,the mask having a hole portion formed with a plurality of hole patternsand a flat portion not formed with a hole pattern; (2) a step of forminga plurality of holes in the insulating film by dry etching based on themask; (3) a step of irradiating light having a continuous spectrum on aflat portion and a hole portion of the film, measuring a change in thewavelength axis direction shift amount between the reflectivity ofdetection light in the flat portion and the reflectivity of detectionlight in the hole portion and calculating the depth of the hole portionbased on the measurement result thereby to control the operation to forma plurality of holes through the insulating film during the step of (2);and (4) a step of burying a metal in the plurality of the holes of thehole portion.
 6. A method for fabricating a semiconductor device asdefined in claim 5, wherein: the light enters a main surface of asemiconductor wafer at right angles or diagonally thereto, and thereflectivity is measured from the ratio of intensity between theincident light and the reflected light during the step (2). 7.(canceled)
 8. (canceled)
 9. A method for fabricating a semiconductordevice as defined in claim 8, wherein the light is incident on a mainsurface of a semiconductor wafer at right angles or diagonally thereto,and a reflectivity thereby is measured from the ratio of intensitybetween the incident light and its reflected light during the step (2).10. A method for fabricating a semiconductor device as defined in claim9, wherein the light is white light.
 11. A method for fabricating asemiconductor device by preparing a plasma etching system including avacuum chamber, a susceptor arranged in the vacuum chamber forinstalling a semiconductor wafer, a gas introducing means forintroducing the material gas to the vacuum chamber and a high-frequencypower introducing means, the method comprising the step of converting toa plasma gas introduced into the vacuum chamber by the gas introducingmeans and forming a plurality of holes selectively on a main surface ofthe semiconductor wafer in a plasma atmosphere, the plasma etchingsystem including a light source for radiating detection light, adetection system having a beam splitter arranged in a light path, alens, a spectrometer and a diode array, an XY movable table movable inhorizontal direction in the detection system and a computer for storingdata of the detection system, and the detection light from the lightsource being radiated on the main surface of the semiconductor waferthrough a quartz window formed in a ceiling portion of the vacuumchamber; and the method further comprising a step of radiating thedetection light from the light source in a flat portion and a holeportion of the main surface of the semiconductor wafer, and measuringthe change in reflectivity in the flat portion and the hole portion,during or after the step of forming the holes.
 12. (canceled) 13.(canceled)
 14. (canceled)
 15. A method of fabricating a semiconductordevice by preparing a plasma etching system including a vacuum chamber,a gas introducing means for introducing the material gas to the vacuumchamber and a high-frequency power introducing means, the methodcomprising the step of converting, by the high-frequency power, to aplasma the gas introduced into the vacuum chamber by the gas introducingmeans and forming a plurality of holes selectively on a main surface ofa semiconductor wafer in a plasma atmosphere, wherein: the plasmaetching system includes an etching depth inspection unit having a firstelectrode arranged in contact with the semiconductor wafer and movablein horizontal direction, a second electrode arranged in opposed relationto first electrode and movable in vertical direction, an impedance meterelectrically connected to first and second electrodes, and a computerelectrically connected to the impedance meter through an A/D converter;the method comprising a step of measuring an electrostatic capacitanceof a flat portion and a hole portion of the wafer on the main surface ofthe semiconductor wafer by the etching depth inspection unit afterforming the holes, and a step of comparing the electrostatic capacitanceacquired from the flat portion and the hole portion with each other anddetermining the difference between a measurement value of theelectrostatic capacitance of the flat portion and a measurement value ofthe electrostatic capacitance of the hole portion.
 16. A method forfabricating a semiconductor device as defined in claim 15, furthercomprising a step of scanning the semiconductor wafer by the secondelectrode for measuring the hole portion, a scanning step determiningthe position of the second electrode in such a manner as to minimize theelectrostatic capacitance.
 17. A method for fabricating a semiconductordevice as defined in claim 15, wherein the plasma etching systemincludes a load lock chamber and an unload lock chamber, and the firstand second electrodes are arranged in the unload lock chamber.
 18. Amethod for fabricating a semiconductor device as defined in claim 15,wherein a plurality of protruded electrodes in contact with the reversesurface of the semiconductor wafer are arranged on the first electrode.19. An apparatus for fabricating a semiconductor device as defined inclaim 15, wherein the forward end portion of the second electrodeconstitutes a circular surface having a diameter of 0.1 mm to 3 mm. 20.A method for fabricating a semiconductor device as defined in claim 15,wherein the interval between the second electrode and the surface of thesemiconductor wafer is between 0.1 μm and 50 μm.